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STA333ML
Sound TerminalTM 2 channel microless high efficiency digital audio system
Target Specification
Features

Wide supply voltage range (4.5-18 V) 2 x 20 W @ 8 , Vcc = 18 V 3 power output configurations; 2 channels of ternary PWM PowerSSO-36 exposed pad package 2 channels of 24-Bit DDX(R) 100 dB SNR and dynamic range 32 kHz to 48 kHz input sample rates Soft volume update Automatic zero-detect mute Automatic invalid input detect mute 2-channel I2S input data interface Selectable clock input ratio (256 / 364 Fs) Max power correction for lower full power 96 kHz internal processing sample rate, 24-bit precision Thermal overload and short-circuit protection embedded
PowerSSO36 slug down
Description
STA333ML is a single die embedding digital audio processing and high efficiency power amplification, capable of operating without the aid of an external micro controller. The STA333ML is part of the Sound TerminalTM family that provides full digital audio streaming to the speaker offering cost effectiveness, low energy dissipation and sound enrichment. The STA333ML combines a unique 24-bit DDX(R) digital Class-D ternary modulator together with an extremely low RDSON stereo power Dmos stage. The latter is capable of a total output power of 2 x 20 W with outstanding performances in terms of efficiency (>90 %), THD, SNR and EMI. The microless feature allows the use in low cost applications (cradle, digital speakers, audio terminals) where no micro controller is needed. The serial audio data interface accepts the world wide used I2S format; basic features (for example, oversampling clock, gain, I2S format) can be set using a minimal number of selection pins. STA333ML is self-protected against thermal overload, overcurrent, short circuit and overvoltage conditions. The fault condition is also exported to an external pin (INT-LINE) for specific requirements.
Applications

LCD DVD Cradle Digital speaker Wireless speaker cradle
Order codes
Part number STA333ML STA333ML13TR Package PowerSSO36 (slug down) PowerSSO36 (slug down) Packing Tube Tape and reel
February 2007
Rev 1
1/15
www.st.com 15
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
Contents
STA333ML
Contents
1 2 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 3.2 3.3 3.4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 5
Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 5.2 5.3 Serial audio interface protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Fault detect recovery bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Zero-detect mute enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 7 8
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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STA333ML
Block diagram
1
Figure 1.
Block diagram
Block diagram
I2S interface
Protection current/thermal Channel 1A
Volume control
Power control DDX
Logic
Channel 1B
Channel 2A
Regulators PLL Bias Channel 2B
3/15
Pin description
STA333ML
2
Pin description
Figure 2. Pin connection (Top view)
GND_SUB FMT TEST_MODE VSS_REG VCC_REG OUT2B GND2 VCC2 OUT2A OUT1B VCC1 GND1 OUT1A GND_REG VDD_REG CONFIG N.C. N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 VDD_DIG GND_DIG GAIN ONSEL INT_LINE RESET SDI LRCKI BICKI XTI PLL_GND FILTER_PLL VDD_PLL PWRDN GND_DIG VDD_DIG N.C. N.C.
D05AU1638
Table 1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12
Pin description
Type Gnd I I I/O I/O O Gnd Power O O Power Gnd Name GND_SUB FMT TEST_MODE VSS VSS_REG OUT2B GND2 VCC2 OUT2A OUT1B VCC1 GND1 Substrate ground 0: I2S format 1: left justified This pin must be connected to GROUND Internal reference at Vcc-3.3 V Internal Vcc reference Output half bridge 2B Power negative supply Power positive supply Output half bridge 2A Output half bridge 1B Power positive supply Power negative supply Description
4/15
STA333ML Table 1.
Pin 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Power GND I Power I GND I I I I I O I
Pin description Pin description (continued)
Type I/O GND Power I Name OUT1A GND_REG VDD_REG CONFIG N.C. N.C. N.C. N.C. VDD_DIG GND_DIG PWDN VDD_PLL FILTER_PLL GND_PLL XTI BICKI LRCKI SDI RESET INT_LINE ONSEL Description Output half bridge 1A Internal ground reference Internal 3.3 V reference voltage Paralleled mode command Not connected Not connected Not connected Not connected Positive supply digital Digital ground Power down Positive supply for PLL Connection to PLL filter Negative supply for PLL PLL input clock, 256 Fs, or 384 Fs I2S serial clock I2S left/right clock I2S serial data channel Reset Fault interrupt Onersampling selector 0: 256 Fs 1: 384 Fs Gain selector 0: 0 dBFs 1: 24 dBFs Digital ground Digital supply
34 35 36
I GND Power
GAIN GND_DIG VDD_DIG
5/15
Electrical specifications
STA333ML
3
3.1
Table 2.
Symbol RTh(j-case) Tsd Tw Thsd
Electrical specifications
Thermal data
Thermal data
Parameter Thermal resistance junction to case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis Min. Typ. 1.5 150 130 20 Max. 2 Unit C/W C C C
3.2
Table 3.
Symbol VCC VL VDD_DIG Top Tstg
Absolute maximum ratings
Absolute maximum ratings
Parameter Power supply voltage (VCCxA,VCCxB) Logic input interface Positive supply digital Operating junction temperature Storage temperature 0 -40 -0.3 Min. Typ. Max. 20 4 4 150 150 Unit V V V C C
3.3
Table 4.
Symbol VS VL VDD_DIG Tamb
Recommended operating condition
Recommended operating condition
Parameter Power supply voltage (VCCxA,VCCxB) Logic Input Interface Positive supply digital Ambient temperature Min. 4.5 2.7 2.7 0 3.3 3.3 Typ. Max. 18.0 3.6 3.6 70 Unit V V V C
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STA333ML
Electrical specifications
3.4
Table 5.
Electrical characteristics
Electrical characteristics (VCC = 18 V,VDD_DIG=3.3 V fsw = 384 kHz, Tamb = 25 C, RL = 8 unless otherwise specified)
Parameter THD = 1 % Output power BTL THD = 10% 20 180 250 10 95 95 5 10 8 8 4.5 PWRDN = 0 PCM Input signal = -60 dBFS. Switching frequency = 384KHz No LC filters 0.1 10 20 10 10 18 m A % % ns ns ns ns V mA Power Pchannel/Nchannel MOSFET (Total Bridge) Power Pchannel/Nchannel leakage Power Pchannel RdsON Matching Power Nchannel RdsON Matching Low current dead time (static) High current dead time (dynamic) Rise time Fall time Supply voltage operating voltage Supply current from Vcc in power down Icc Supply current from Vcc in operation Conditions Min. Typ. 16 W Max. Unit
Symbol Po
RdsON ldss gP gN ILDT IHDT tr tf VCC
ld=1A Vcc = 18V ld=1A ld=1A Resistive load Figure 3. @lload = 1.5 A (Figure 5) Resistive load Figure 3. Resistive load Figure 3.
30
mA
Supply current DDX processing Internal clock = 49.152 MHz (reference only) Ilim Isc UVL tmin DR SNR THD+N Overcurrent limit short circuit protection Under voltage protection threshold Output minimum pulse width Dynamic range Signal to noise ratio Total harmonic distortion + noise Power supply rejection ratio A - weighted Po = 1 W, f = 1 kHz DDX stereo, <5 kHz Vripple = 1 VRMS Audio input = dither only No load 20 Nonlinear output Hi-Z output 2.2 2.7
80 3.5 3.8 3.5 30 100 94 0.05 0.2 4.3 5.0 4.3 60
mA A A V ns dB dB %
PSRR
80
dB
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Electrical specifications Table 5.
STA333ML
Electrical characteristics (continued) (VCC = 18 V,VDD_DIG=3.3 V fsw = 384 kHz, Tamb = 25 C, RL = 8 unless otherwise specified)
Parameter Crosstalk Peak efficiency, DDX mode Conditions DDX stereo, <5 kHz One CH driven @ 1 W other channel measured Po = 2 x 20 W, 8 Min. Typ. 80 90 Max. Unit dB %
Symbol XTALK
Table 6.
Functional pin status
Pin number 23 23 0 1 Logic value IC status Low absorption Normal operation
Pin name PWRDN PWRDN
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STA333ML
Testing
4
Testing
Figure 3. Resistive load
OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTxY
M57
DTf
INxY
R 8
+ -
V67 = vdc = Vcc/2
D03AU1458
gnd
Figure 4.
Test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC
Duty cycle=A
DTout(A) M58 Q1 OUTA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTB M64
Duty cycle=B
DTin(A) INA M57
DTin(B) INB M63
Iout=4A Lout = 1.5 A Q3
Iout=4A Lout = 1.5 A Q4
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4A in the direction shown in figure
D03AU1517
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Functional description
STA333ML
5
5.1
Functional description
Serial audio interface protocols
Figure 5. I2S
Lrclki
Bicki
Sdi
1 3 123
n-1 n
123
n-1 n
Figure 6.
Left justified
Lrclki/ Lrclko
Biclki/ Biclko
Sdatai/ Sdatao
123
n-1 n
123
n-1 n
5.2
Fault detect recovery bypass
The on-chip STA333ML power output block provides feedback to the digital controller using inputs to the power control block. The FAULT input is used to indicate a fault condition (either over-current or thermal). When FAULT is asserted (set to 0), the power control block attempts a recovery from the fault by asserting the tristate output (setting it to 0 which directs the power output block to begin recovery), holds it at 0 for 1 ms and then toggles it back to 1. This sequence is repeated for as long as the fault exists.
10/15
STA333ML
Functional description
5.3
Zero-detect mute enable
If this function is enabled, the zero-detect circuit examines each processing channel to see if 2048 consecutive zero value samples (regardless of fs) are received. If so the channel is muted.
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Package thermal characteristics
STA333ML
6
Package thermal characteristics
A thermal resistance of 25 C per Watt can be achieved using a ground copper area of 3 x 3 cm, and using 16 vias, on the PCB (see Figure 7). The amount of power dissipated within the device depends primarily on the supply voltage, load impedance and output modulation level. The max estimated dissipated power for the STA333ML is 3 W. This gives, with the suggested board copper area, a maximum Tj of 75 C. This gives a safety margin before the thermal protection intervention is invoked (Tj=150 C) in consumer environments where a 50 C is the maximum ambient temperature. Figure 7. Thermal characteristic
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STA333ML
Package information
7
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 8. PowerSSO36 exposed pad mechanical data and package dimensions
DIM. A A2 a1 b c D (1) E (1) e e3 F G G1 H h k L M N O Q S T U X Y MIN. 2.15 2.15 0 0.18 0.23 10.10 7.4 0.5 8.5 2.3 0.10 0.06 10.50 0.40 5 0.55 4.3 10 1.2 0.8 2.9 3.65 1.0 4.1 6.5 4.7 7.3 0.161 0.256 0.047 0.031 0.114 0.144 0.039 0.185 0.287 0.90 0.022 0.169 10 mm TYP. MAX. 2.47 2.40 0.075 0.36 0.32 10.50 7.6 MIN. 0.084 0.084 0 0.007 0.009 0.398 0.291 0.019 0.335 0.090 0.004 0.002 0.413 0.016 5 0.035 inch TYP. MAX. 0.097 0.094 0.003 0.014 0.012 0.413 0.299
OUTLINE AND MECHANICAL DATA
10.10
0.398
(1) "D" and "E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per side(0.006")
PowerSSO-36 (exposed pad)
A2
A
hx45
G
LEAD COPLANARITY
A
D
e
stand-off
a1
T
Y
Gauge plane 0.25
L
O
H E X
F
U
B
0.1 M A B
b e3
S
BOTTOM VIEW
7587131 A
k
c
Q
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Revision history
STA333ML
8
Revision history
Table 7.
Date 1-Feb-2007
Document revision history
Revision 1 Initial release. Changes
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STA333ML
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